1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an LDD structure with minimal lateral dopant diffusion in the fabrication of integrated circuits.
2. Description of the Prior Art
As the physical geometry of semiconductor devices shrinks, the channel length of the transistor is reduced as well. This leads to serious short channel effects. Since boron has a high diffusivity in the silicon substrate, lateral dopant diffusion is quite prominent when boron is used as the dopant for a PLDD structure. This lateral dopant diffusion will affect the threshold voltage and transistor current drive, thus affecting the device performance. In the traditional process flow, PLDD implantation is performed prior to source/drain implantation and annealing. The annealing process will enhance boron diffusion from the PLDD area into the channel underlying the gate electrode, causing the problems mentioned above.
U.S. Pat. No. 5,969,398 to Murakami teaches plasma doping of the gate and source/drain regions. U.S. Pat. Nos. 5,866,460 and 5,998,274, both to Akram et al teach a method to form source and drain subregions each having a different dopant concentration in a polycide process. U.S. Pat. No. 5,913,112 to Yamazaki et al discloses formation of LDD regions after the gate has been oxidized. The oxidized portion of the gate acts as a mask for the LDD implantation.